Add ARM11 support for Oprofile.

Patch is the same as [1] provided in "[PATCH] arm/arm11 support"[2], by
Riku Voipio, adapted to apply to CVS (2007-05-22).

[1] http://osdir.com/ml/oprofile/2006-10/txt3cnZHOa4DW.txt,
[2] provided in http://osdir.com/ml/oprofile/2006-10/msg00091.html


diff --exclude=CVS --exclude='*~' --exclude='.#*' -Naur oprofile/events/Makefile.am oprofile_with_arm11/events/Makefile.am
--- oprofile/events/Makefile.am	2007-05-22 14:04:01.000000000 -0300
+++ oprofile_with_arm11/events/Makefile.am	2007-05-22 12:16:20.000000000 -0300
@@ -29,6 +29,7 @@
 	x86-64/family10/events x86-64/family10/unit_masks \
 	arm/xscale1/events arm/xscale1/unit_masks \
 	arm/xscale2/events arm/xscale2/unit_masks \
+	arm/arm11/events arm/arm11/unit_masks \
 	mips/20K/events mips/20K/unit_masks \
 	mips/24K/events mips/24K/unit_masks \
 	mips/25K/events mips/25K/unit_masks \
diff --exclude=CVS --exclude='*~' --exclude='.#*' -Naur oprofile/events/arm/arm11/events oprofile_with_arm11/events/arm/arm11/events
--- oprofile/events/arm/arm11/events	1969-12-31 21:00:00.000000000 -0300
+++ oprofile_with_arm11/events/arm/arm11/events	2007-05-22 12:16:20.000000000 -0300
@@ -0,0 +1,21 @@
+# ARM11 events
+#
+event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
+event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
+event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
+event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses
+event:0x05 counters:1,2 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
+event:0x06 counters:1,2 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted
+event:0x07 counters:1,2 um:zero minimum:500 name:INSN_EXECUTED : instructions executed
+event:0x09 counters:1,2 um:zero minimum:500 name:DCACHE_ACCESS : data cache access, cacheable locations
+event:0x0a counters:1,2 um:zero minimum:500 name:DCACHE_ACCESS_ALL : data cache access, all locations
+event:0x0b counters:1,2 um:zero minimum:500 name:DCACHE_MISS : data cache miss
+event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
+event:0x0d counters:1,2 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch
+event:0x0f counters:1,2 um:zero minimum:500 name:TLB_MISS : Main TLB miss
+event:0x10 counters:1,2 um:zero minimum:500 name:EXP_EXTERNAL : Explict external data access
+event:0x11 counters:1,2 um:zero minimum:500 name:LSU_STALL : cycles stalled because Load Store request queque is full
+event:0x12 counters:1,2 um:zero minimum:500 name:WRITE_DRAIN : Time swrite buffer was drained
+event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
+# 
diff --exclude=CVS --exclude='*~' --exclude='.#*' -Naur oprofile/events/arm/arm11/unit_masks oprofile_with_arm11/events/arm/arm11/unit_masks
--- oprofile/events/arm/arm11/unit_masks	1969-12-31 21:00:00.000000000 -0300
+++ oprofile_with_arm11/events/arm/arm11/unit_masks	2007-05-22 12:16:20.000000000 -0300
@@ -0,0 +1,4 @@
+# Arm11 possible unit masks
+#
+name:zero type:mandatory default:0x00
+	0x00 No unit mask
diff --exclude=CVS --exclude='*~' --exclude='.#*' -Naur oprofile/libop/op_cpu_type.c oprofile_with_arm11/libop/op_cpu_type.c
--- oprofile/libop/op_cpu_type.c	2007-05-22 14:04:03.000000000 -0300
+++ oprofile_with_arm11/libop/op_cpu_type.c	2007-05-22 12:17:06.000000000 -0300
@@ -69,6 +69,7 @@
 	{ "ppc64 Cell Broadband Engine", "ppc64/cell-be", CPU_PPC64_CELL, 8 },
 	{ "AMD64 family10", "x86-64/family10", CPU_FAMILY10, 4 },
  	{ "ppc64 PA6T", "ppc64/pa6t", CPU_PPC64_PA6T, 6 },
+	{ "ARM11 PMU", "arm/arm11", CPU_ARM_ARM11, 3 }
 };
  
 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
diff --exclude=CVS --exclude='*~' --exclude='.#*' -Naur oprofile/libop/op_cpu_type.h oprofile_with_arm11/libop/op_cpu_type.h
--- oprofile/libop/op_cpu_type.h	2007-05-22 14:04:04.000000000 -0300
+++ oprofile_with_arm11/libop/op_cpu_type.h	2007-05-22 12:17:28.000000000 -0300
@@ -67,6 +67,7 @@
 	CPU_PPC64_CELL, /**< ppc64 Cell Broadband Engine*/
 	CPU_FAMILY10, /**< AMD family 10 */
  	CPU_PPC64_PA6T, /**< ppc64 PA6T */
+	CPU_ARM_ARM11, /**< ARM11 */
 	MAX_CPU_TYPE
 } op_cpu;
 
diff --exclude=CVS --exclude='*~' --exclude='.#*' -Naur oprofile/libop/op_events.c oprofile_with_arm11/libop/op_events.c
--- oprofile/libop/op_events.c	2007-05-22 14:04:04.000000000 -0300
+++ oprofile_with_arm11/libop/op_events.c	2007-05-22 12:23:41.000000000 -0300
@@ -783,6 +783,7 @@
 			break;
 
 		// we could possibly use the CCNT
+		case CPU_ARM_ARM11:
 		case CPU_ARM_XSCALE1:
 		case CPU_ARM_XSCALE2:
 			descr->name = "CPU_CYCLES";
diff --exclude=CVS --exclude='*~' --exclude='.#*' -Naur oprofile/utils/ophelp.c oprofile_with_arm11/utils/ophelp.c
--- oprofile/utils/ophelp.c	2007-05-22 14:04:05.000000000 -0300
+++ oprofile_with_arm11/utils/ophelp.c	2007-05-22 12:18:44.000000000 -0300
@@ -419,6 +419,9 @@
 		printf("See Alpha Architecture Reference Manual\n"
 		       "ftp://ftp.compaq.com/pub/products/alphaCPUdocs/alpha_arch_ref.pdf\n");
 		break;
+	case CPU_ARM_ARM11:
+		printf("See ARM11 Technical Reference Manual\n");
+		break;
 	case CPU_ARM_XSCALE1:
 	case CPU_ARM_XSCALE2:
 		printf("See Intel XScale Core Developer's Manual\n"